Generally, the semiconductor memory device is supplied with an external voltage VDD and a ground voltage VSS from the outside and generates an internal voltage which is necessary for an internal operation. As the voltage which is necessary for the internal operations of the semiconductor memory device, a core voltage VCORE supplied to a memory core region, a high voltage VPP used to drive or overdrive a word line, a back bias voltage VBB supplied as a bulk voltage of NMOS transistor in the core region, and a bitline pre-charge voltage VBLP supplied to a bit-line pair BL, BLB during a precharge operation.
Herein, the core voltage Vcore may be supplied by reducing the external voltage VDD at a certain level. However, since the high voltage VPP maintains a level higher than the power source voltage VDD inputted from the outside, and the back-bias voltage VBB maintains a level lower than the power source voltage VDD input from the outside, a charge pump circuit is needed to supply charges for high voltage VPP and the back-bias voltage VBB in order to supply the high voltage VPP and the back-bias voltage VBB respectively.
FIG. 1 is a graphical diagram showing an external voltage and an internal voltage used for a general semiconductor memory device.
As shown in FIG. 1, after applying the power source to the semiconductor memory device, since a level of the internal voltage (high voltage VPP, core voltage VCORE, bit-line precharge voltage VBLP) is increased until it reaches a prescribed level in accordance with a level of the external voltage VDD, a procedure of stabilizing the level of the internal voltage is needed before a normal operation such as a read or write operation is initialized. Therefore, according to prior semiconductor memory device, the level of the internal voltage is stabilized and thus the normal operation is performed through an initialization operation.
Hereinafter, it will be described on the initialization operation according to a specification of a mobile DDR DRAM shown FIG. 2 for each of time sections shown in FIG. 1.
First, as the level of the external voltage VDD increases, the level of the internal voltage also increases, during a section of 0˜t1 sec. Next, the semiconductor memory device becomes NOP state or a deselect state in order to stabilize the clock signal, during a section of t1˜t2 sec. The clock signal stabilizing section is determined as approximately 200 μsec.
Next, during a section of t2˜t3, the precharge operation is performed for all banks included in the semiconductor memory device and an auto-refresh operation is performed 2 times. Further, a mode register and an extended mode register are set during this section. Then, the normal operations of the semiconductor memory device are carried out at a section after t3 sec.
However, with respect to a recent semiconductor memory device, it tends to omit the 2-times auto-refresh operation which has been performed at the section of t2˜t3 sec. Therefore, there is a need for a scheme capable of stabilizing the internal voltage even though the auto-refresh operation is omitted during the initialization operation.